Example embodiments relate to a phase locked loop, and more particularly, to a phase-rotating phase locked loop that has a controller for controlling a dual phase frequency detector.
As a data rate in chip-to-chip communication gradually increases, completely recovering clock and data at a receiver is receiving more attention.
Many studies on a PLL topology that simultaneously generates and adjusts multi-clock phases for a phase-interpolation based clock data recovery (CDR) application have been conducted in consideration of high performance and low consumption power.
In the case of a dual phase frequency detector (PFD) phase-rotating PLL (DP-PLL) that has two PFDs, when implementing a phase interpolation function in the PLL, phase interpolation errors may frequently occur due to the two PFDs.